1. Field of the Invention
The present invention relates to a solid-state imaging apparatus.
2. Description of the Related Art
In recent years, the number of pixels of a solid-state imaging apparatus has been increased for enhancement of the quality of photographed images, in an image input apparatus such as a digital still camera and a digital video camera. Further, the solid-state imaging apparatuses, which are loaded with A/D converters to realize digital output, come out.
As one example of the A/D conversion type which is loaded on a solid-state imaging apparatus, there is a column A/D conversion type. As the prior art document, Japanese Patent Application Laid-Open No. H05-48460 (Patent Document 1) is cited. Its circuit configuration is illustrated in the drawing.
A column A/D conversion type has A/D converters 9 at respective columns of pixels and operates them in parallel, and therefore, can enhance the speed of readout of a solid-state imaging apparatus. Meanwhile, with miniaturization of pixels, serious limitations in layout are posed to the A/D converters 9 arranged at the respective columns. The configuration of a column A/D converter generally has a common counter 5 and lamp signal generating circuit, and has in each row, a comparison circuit of a sensor signal and a lamp signal, and an accumulation unit which stores data from the counter when the comparison circuit performs comparison and determination. When the number of bits of A/D conversion increases for enhancement of image quality, if processing is to be performed in the same period of time as the case where the number of bits is increased, the operation speed of the counter needs to be increased proportionally to the power of two.
Further, in the sensor loaded with column A/D converters, during A/D conversion of sensor output of a certain row, the A/D conversion data of the previous row is output, for enhancement of operation speed, and therefore, the accumulation unit which holds the conversion data of the previous row is required.
FIG. 1 of Japanese Patent Application Laid-Open No. H05-48460 is illustrated in FIG. 8. The configuration disclosed in FIG. 8 has the problem of increase in the width between the pixels because a plurality of accumulation units is arranged in the direction along the row.